Extended Converter Systems

AIMORA provides a reusable fixed-step instantaneous-EMT converter-system library with explicit family, fidelity, topology, modulation, application, event, state, provenance, validity and typed result contracts. Every admitted family/fidelity intersection executes through the same public preparation API and the activated production backend; an unsupported selection returns typed readiness instead of silently changing family, topology or fidelity.

Released boundary

The stable standalone boundary contains 22 families and 52 executable family/fidelity intersections. The complete public matrix is generated by converter_executable_fidelities, so the accepted and unsupported combinations cannot drift from the public API.

AverageValue retains power-consistent ports, physical passive/DC/control state and declared low-frequency outputs but owns no individual switching edge, device stress or switching spectrum. SwitchingStateEquivalent retains exact ordered ideal valve states, carrier or firing calendars, topology-dependent connections, passive/DC state and commutation transitions while omitting junction, recovery, tail and thermal physics. SwitchingDetailed composes the accepted bridge graph with selected detailed devices and retains junction charge, reverse recovery, turn-off tail, switching energy, electrothermal state, snubbers, events, loss and stress.

The five application compositions are released at average-value fidelity around the three-phase two-level grid-interface family. An application label coordinates already-released converter, passive and transformer stages and adds application outputs; it does not create a private local solver or claim later plant, FACTS, HVDC or MMC physics.

Selection and readiness

Construct a ConverterSystemSelection with one exact ConverterSystemFamily, ModelFidelity, application and compatible phase, pulse, channel, cell and thermal-stage counts. Bind it in a ConverterSystemSpecification together with ordered port definitions, exact topology and device signatures, passive or transformer signatures, rated bases, fixed-step timing, modulation parameters, provenance, validity and an optional exact event calendar.

Use converter_family_category, converter_executable_fidelities and converter_supported_modulations to inspect the public boundary before construction. Use converter_system_readiness for the complete typed admission check, then call prepare_converter_system, advance_converter_system! and execute_converter_system! through an explicitly activated backend. Public package loading and readiness inspection do not require or reveal the private solver.

using AIMORA

family = AIMORA.ConverterSystems.BuckChopper
fidelities = AIMORA.ConverterSystems.converter_executable_fidelities(family)
modulations = AIMORA.ConverterSystems.converter_supported_modulations(family)

The runnable emt_extended_converter_systems case shows complete construction and execution without depending on a private fixture path.

Physical equations and signs

Every switching-state or switching-detailed system stamps its oriented bridge, device, passive and transformer graph into the global nodal transaction and satisfies branch voltage compatibility, nodal KCL, every selected constitutive residual and the declared stored-energy balance within its preregistered fixed-step tolerance. Current is positive into each named converter port and passive power is positive into the converter; exported power and application delivery use separately named result fields.

The continuous-conduction ideal limits are Vout/Vin=d for buck, Vout/Vin=1/(1-d) for boost and Vout/Vin=-d/(1-d) for the inverting buck-boost, but production execution solves the physical inductor, capacitor, source, load and switching state rather than imposing those limits. Interleaved channels retain the exact carrier offset 2π(k-1)/N, and the dual-active bridge retains its two bridges, isolation transformer, leakage current, DC state and signed phase-shift transfer.

Natural diode conduction follows terminal voltage and holding rules, while thyristor families combine firing delay, latching, holding and natural current-zero turn-off. Multilevel results retain neutral-point, flying-capacitor or cell charge as applicable. The matrix converter uses an explicit Boolean 3x3 incidence state that connects every output to exactly one input while prohibiting input short circuits and inductive-output interruption; the cycloconverter retains positive and negative bridge groups, firing, interlock and natural commutation.

Modulation, events and continuation

The released modulation surface contains natural diode commutation, phase-controlled firing, carrier SPWM, space-vector PWM, phase-shifted carrier PWM, selective harmonic elimination, nearest-level modulation, single/dual/triple-phase-shift DAB methods, matrix space-vector modulation and cycloconverter firing synthesis only where each family admits them. Carrier, firing, sample, write, delayed release, protection, source and output calendars use exact fixed-step logical time and stable same-instant priority.

The public physical buck case declares a controlled-path block at 120 microseconds and restart at 180 microseconds. Its mid-run portable snapshot restores into a newly prepared runtime and must reproduce every waveform, event and final deterministic signature exactly. No accepted history, task, event, output or energy accumulator advances on a rejected trial.

Results and evidence

ConverterSystemResult records the versioned schema, exact specification identity, family, fidelity, application, acceptance status, typed physical state, event records, KCL, charge and energy residuals, harmonics, warnings and deterministic signature. Fidelity-specific traces add physical waveforms, valve state, passive and transformer state, modulation or firing data, detailed-device state, losses and application delivery quantities.

The public case commits an 81-row matrix containing all 66 standalone and 15 application fidelity candidates, including 24 explicit unsupported rows. It also commits a physical switching-detailed buck waveform, result contract, summary and two curated SVG plots. Complete all-family execution is independently qualified outside the public case: 52 standalone intersections and five applications execute with split restart, refinement, physical residuals and deterministic signatures; pinned OpenModelica overlap covers the registered AC/DC, DC/DC and DC/AC subset; adversarial evidence kills every preregistered critical mutation; and P0–P2 exercises the same fidelity and output boundary at increasing scale.

Public validity and limitations

The aggregate native-Linux domain is finite SI-peak fixed-step EMT: terminal voltage from 100 mV through 1 MV, current from 1 mA through 100 kA, generic rating from 1 W through 100 MVA, fundamental frequency from 1 Hz through 1 kHz, switching or firing frequency from 100 Hz through 200 kHz, multipulse count through 24, two through eight interleaved channels or cascaded cells and one through eight detailed thermal stages. Each concrete family and parameter set narrows that aggregate domain, and switching execution must resolve its carrier, device and event dynamics and pass refinement.

Average-value results never claim individual switching ripple, edge timing or device stress. Uncovered external families retain independent AIMORA evidence without an external-equivalence claim. The library does not establish manufacturer prediction, product design, arbitrary topology synthesis, destructive failure, renewable-plant, FACTS, HVDC or MMC behavior, field validity, ATP/PSCAD equivalence, protected-standard conformance, safety, HIL qualification or certification.